Pulsic to Introduce Integrated, Full-chip Planning and Top-level Routing Solution for Custom IC Design at DAC 2011
Pulsic Planning Solution components enable automated top down and bottom up hierarchical floor planning for custom and multicore design
san jose, calif., June 1, 2011 —Pulsic, the premier provider of physical design tools for custom design automation, will introduce the Pulsic Planning Solution™ at DAC 2011 in San Diego. A completely integrated full-chip solution built ‘from the ground up’ for custom, analog and mixed-signal (AMS) integrated circuits (ICs), the Pulsic Planning Solution automates planning and top-level routing functionality. The Pulsic Planning Solution — comprised of components for chip planning, power planning, bus and repeater cell planning, and signal planning — is based on Pulsic’s innovative and well-established Unity™ technology, in use by leading design companies worldwide for over 10 years.
The Pulsic Planning Solution is Pulsic’s response to users encountering bottlenecks as custom design complexity continues to increase dramatically. Large, complex custom IC designs and the complexity of top-level floorplanning (and the number of signals to be planned and routed) are forcing digital design teams to spend ever more time and resources in order to complete floorplans and DRC-correct top level integration. Getting large custom ICs to tape out more quickly with existing ASIC tools, however, is problematic. Although such tools are powerful, their lack of configurability often makes it impossible to complete finer tasks, such as bus/repeater cell planning and insertion or DRC/ LVS top level routing. In most cases, semiconductor companies must license the whole flow as a single ‘seat’ from an ASIC tool vendor when individually licensed components would provide a more efficient solution and a more economical use model.
Grounded in Pulsic’s Unity technology, Pulsic Planning Solution is the first complete planning tool suite to enable top down and bottom up hierarchical floorplanning for custom ICs. Understanding that customers need flows, not just technologies, Pulsic combines innovative technology into guided flows that help even non-expert users achieve best solutions in minimum time. The Pulsic Planning Solution guides users through the entire floorplanning process, from initial blackbox (or prototype) floorplanning through to the final layout. The flow encompasses all the necessary steps and allows users to quickly adopt each netlist revision and engineering change order (ECO). In Pulsic Planning Solution, a truly hierarchical platform, all components are integrated with each other and with real custom design flows, OpenAccess (OA), Cadence (CDBA) and industry standard (LEF/DEF/Verilog).
“As design complexity increases, custom and multicore designers and layout engineers have been finding that the traditional bottom-up layout assembly methods, or existing tools that are primarily designed for large digital ASICs, are not keeping pace with productivity demands,” said Mark Williams, founder and CEO of Pulsic. “Each component of the Pulsic Planning Solution has two advantages: technological advances provide increased productivity, and each can be purchased in any combination, making critical functionality highly configurable for each member of the design team.”
Technological Advantages of the Pulsic Planning Solution
Users get the full benefit of Pulsic technology and experience with minimum training and maximum productivity.
All products are completely integrated, with a single executable, removing data translation issues and maximizing productivity.
Engineering change orders
At the core of the Pulsic Planning Solution is Unity’s ECO technology, which allows rapid adoption of changes and new revisions into the design without the need to start again. ECO technology ensures that previous work is never wasted and that designers always have a head start on the next revision.
Custom design-focused technology
The features and constraints required by custom design are built into the technology, giving optimum results first time. Users no longer have to struggle to adapt ASIC technology for custom design.
Components of the Pulsic Planning Solution
Unity™ Chip Planner – Hierarchical Floorplanning for Custom Designs
Fully hierarchical planning capability with rapid prototyping, area estimation, block placement, intelligent pin placement and optimization and incremental hierarchical ECO capability.
Unity™ Power Planner – Automated Power Planning and Power Grid Generation for Multiple Power Domains
A guide-driven capability for automatic generation of constraint aware, multi-domain power grids that accommodates ECOs using re-usable power grid guides.
Unity™ Bus Planner – Bus Planning/Routing and Repeater Cell Planning/Insertion
A GUI-based, guide-driven methodology for planning and inserting large numbers of very wide bit buses, complete with fully configurable bus interleaving capabilities, integrated with buffer planning and insertion functionality.
Unity™ Signal Planner — Hierarchical Signal Planning and Routing for Custom Designs
The first and only product to offer truly hierarchical, automated signal planning and routing, enables fast, constraint-driven routing of today’s advanced custom designs.
The Pulsic Planning Solution can be used either as a complete standalone flow for planning or individual components can be used in a traditional digital flow. For example, the Unity Bus Planner provides functionality that ASIC tools don’t provide, and can be used as a point solution in an existing custom or ASIC flow interoperating with other tools.
CDA is a registered trademark and Unity, UniPlan. UniPlace, UniRoute, UniEdit, Pulsic Planning Solution, Unity ™ Chip Planner, Unity™ Bus Planner, Unity™ Power Planner, and Unity™ Signal Planner are trademarks of Pulsic Limited. Any other trademarks or trade names mentioned are the property of their respective owners.
Michelle Clancy, Cayenne Communication LLC