Custom Design Automation Leader Pulsic Granted Patent For Routing According To Current Density Rules
Optimal Net Widths Achieved Through Automatic Routing Leads to Lower IR losses, Elimination of Electro-Migration Issues, and Smaller Designs
Bristol, England – July 2nd, 2009 – Pulsic Limited, the leader in custom design automation (CDA®), today announces that it has been granted US Patent (11383658) for a unique routing innovation incorporated in its market-leading physical chip design software. This important patent, titled “Automatic routing nets according to current density rules”, protects unique technology incorporated in Pulsic’s UniRoute automated router.
By taking into account the current required by the individual branches in a net, UniRoute is able to optimise a net’s width. This innovation creates the smallest net width that satisfies the electro-migration rules for current density. Optimising the net widths not only eliminates the risk of electro-migration but also significantly reduces IR losses and minimises routing area. For layout engineers, this eliminates the need to estimate current densities and manually calculate varying net-widths for high fan-out interconnects.
Mark Waller, Vice President of Research and Development for Pulsic, said, “Without this technique, nets are either over-engineered and so take up too much area, or manual intervention causes current density rule violations that need to be fixed late in the design cycle. UniRoute’s unique approach optimises net width during automatic routing, taking into account current needs throughout the net and reducing branch sizes accordingly.”
UniRoute is part of Pulsic’s flagship product Unity™, a complete custom design automation solution for the physical design of high volume ICs. Unity combines three other key components – UniPlan™ (hierarchical floorplanning), UniPlace™ (placement) and UniEdit™ (editing) – with timing, signal integrity, ECO and DFM functionality to provide a truly unique design environment.
Unity has been designed to increase productivity, decrease design area and increase yield for even the most challenging custom digital, mixed-signal and analog IC designs.