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Products & Solutions

Unity Chip Planner

The First and Only Hierarchical Floorplanner for Custom Designs

Pulsic Unity Chip Planner, the first truly hierarchical floorplanner built for custom design, enables custom design teams to manage growing complexity while accelerating design closure and improving design quality.



Made-for-Custom Floorplanning

Custom designers face unique challenges such as large hard-IP blocks, analog content, few metal layers available for routing. At leading-edge nodes (28 nm and below), process rules constrain designs in new ways, and the extreme aspect ratios of the routed wires and highly resistive metals make understanding parasitics critical. Pulsic has applied insights gained in over 10 years of work with leading-edge custom designers to develop Unity Chip Planner to address the unique needs of custom design.


Complex Chips Need a New Approach

Automated, hierarchical floorplanners are a standard part of the digital design flow. However, they don’t address the unique needs of custom design. So, until now, many custom design teams have struggled with bottom-up, manual assembly methodologies that lack a global understanding of a chip’s routing congestion and top-level parasitic data for simulation until the chip is almost complete. With these manual approaches, lack of automation and hierarchy management waste design effort and silicon resource. The frequent netlist changes that are a natural part of a  leading-edge design process are difficult to manage manually and can cause major delays.


Faster Design Closure and Successful Results – Every Time

By providing a high level of automation, Unity Chip Planner gives accurate results quickly and enables custom design teams to respond to netlist changes quickly and easily. Unity Chip Planner provides all the necessary tools and technologies within a fully integrated floorplanning environment. The guided flow offered in Unity Chip Planner helps ensure faster design closure with successful results, every time.


Benefits

  • Achieve design closure faster with the first and only top down hierarchical floorplanner for custom design
  • Explore options and implement floorplans rapidly with accurate area and parasitic data
  • Obtain accurate parasitics for early simulation and static timing analysis
  • Execute ECOs quickly and precisely.


Features

  • Hierarchical and pseudo-hierarchical floorplanning for custom design
  • Hierarchical area estimation, including custom digital and analog estimation
  • Automatic block placement and softblock shaping
  • Hierarchical automatic pin placement and sorting optimization
  • Intelligent, router-aware pin placement for efficient top-level routing
  • (more)


Hierarchical Context

Efficient, effective custom design floorplanning requires a series of top-down optimizations, followed by a bottom-up optimization, that determine pin placement in consideration of the block placement at lower levels of hierarchy, then use those pin placements as the backbone of communication between levels of hierarchy.


Rapid Floorplan Prototyping

Tight design cycles rarely afford custom designers the time to explore different floorplans to find the best fit for the die area. The Unity Chip Planner has a flexible and easy-to-configure interface that enables designers to explore different packages and to prototype multiple floorplan topologies quickly to find the optimal use of the die area allocated for the design.


Best-in-Class Features

The Unity Chip Planner area estimation technology analyses the netlist and hierarchically determines the area required for hard IP, analog blocks, softblocks and multiple standard-cell form factors concurrently.

The Unity Chip Planner router supports complex routing topologies for top-level interconnect and shielding. Pin placement is optimized to enable the ideal routing pattern for every net.

The Unity Chip Planner block placement technology can place hard IP and softblocks simultaneously. The unique “push down” feature makes top-level routing and power-bus structures visible throughout the layout hierarchy.

The Unity Chip Planner hierarchical ECO feature enables designers to propagate changes throughout their design hierarchy rapidly by simply loading the new netlist.