Pulsic advances placement and routing technology
* Latest release of Lyric adds unique placement capabilities
* Clustered layout for mixed-signal and custom digital designs
* Row Compaction, Bias by Area and Pattern Tidy also added
Bristol, England – April 26th, 2006 – Pulsic Limited, the EDA company that delivers shape-based, IC physical design solutions for analog, mixed-signal and custom digital designs, today announced the launch of its advanced placement technology with the roll out of the latest version of Lyric 4-10.
High volume IC design is a highly specialist arena where yield, area and performance are key commercial priorities. Pulsic’s products collectively provide the most comprehensive and focused solution for the physical design of constraint critical devices.
In Lyric 4-10, placement technology is enhanced in a number of ways to accommodate the special needs of these designs; in particular, for irregular sized cells and cell clustering. This cluster placement method enables logically coupled cells to be identified and clustered together in the final layout. This enables the matching of characteristics between repeated sections and a tight control of performance characteristics.
Major new features of Lyric 4-10 include:
- Advanced Placement
- Row Compaction
- Bias by Area
- Pattern Tidy
The advanced placement features incorporate the ability to place all devices within any logical group tightly together (‘clusters’) and also to place groups of groups together (‘cluster of clusters’). This is especially useful in mixed-signal and custom digital designs, where hierarchical clustering placement is often required when physically implementing a part-flattened or fully-flattened design, so that all the devices are geometrically placed according to their instance hierarchy. The ability to handle such design driven requirements is a unique feature in current automatic placement technology. Hierarchical clustering can be derived seamlessly from the schematic into Lyric 4-10, or the tool can automatically deduce the hierarchy from the complete cell instance information.
Another feature incorporated into the new advanced placement bundle is the ability to handle double-height cells. For digital designs, where there are abutting rows of regular devices, the placement engine can now handle double height cells (i.e. twice the placement row height of regular devices) alongside regular sized cells, simultaneously. The placer can also optimize the space neighboring the double height cells to help regular devices achieve the most compact and efficient designs.
Row compaction allows the tool to adjust spacing between rows of cells so that the area is minimized and the design is routable. This is particularly useful in designs with few metal layers and extreme aspect ratios, something common in the memory and imaging markets.
Bias by area allows routing to be constrained and biased in a certain direction within a specified area. This means areas can have a horizontal bias, while other areas have a vertical bias. This feature allows users to deliver the smallest areas when working with a limited number of layers, as is common in memory and other cost sensitive products.
The pattern tidy feature enables powerful pattern improvement in existing wiring, using either the built in pattern set or a set provided by the user. It can be used to improve yield by removing poor routing patterns or freeing space, so higher density designs can be achieved.
Mark Waller, VP Engineering, stated, “Version 4-10 builds on our successful shape-based tool set and continues to deliver critical benefits for high-volume device designers. These features are all customer driven and we are able to satisfy these requirements by rapidly adapting to their methodologies and design flows.”