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Products & Solutions

Pulsic Animate™

Analog Design Automation: The Productivity and Quality Gap

As analog designers target process nodes 90nm and below, the complexities of layout are making analog design automation a necessity. Issues such as layout-dependent effects (LDE), electro-migration (EM), voltage drop (IR) and noise coupling have greater impact at smaller nodes. Automation can ensure correct-by-construction layouts in a fraction of the time it currently takes to do layout manually.

There has been vast progress over the last 30 years in digital layout automation, which has made it possible to develop complex digital ICs relatively quickly. However, for analog layout, techniques are still much the same as they were years ago. There have been some improvements such as parameterized cells to generate DRC correct primitive devices, but placing them and carrying out signal routing remains largely a manual step. EDA progress in analog layout has stalled, despite the vastly increased computing power available today.

Animate Delivers Quality of Layout Demanded by Analog Designers

A major reason for the lack of progress in analog automation has been a general reluctance of analog layout engineers to approve layout generated by automated tools. Consulting layout engineers, even in the same company, will provide differing views as to what is ‘correct’. Therefore, interaction with the layout result is often needed to deliver the quality of layout an experienced analog engineer demands.

Animate provides a “Blueprint” editor, so that the engineer can manipulate the automatically generated layout at a higher level of abstraction than the polygon level. Gone is the need to resort to time consuming manual polygon-level editing. The user can just drag and drop items, or structures, to create a different layout topology triggering the Animate Polymorphic engine to automatically recreate the full layout details.

Editor screenshot of a single placed layout

Animate Delivers Productivity Gain for Analog Designers

In a traditional design flow, a circuit design engineer will send schematics and constraints to the layout designer, who in turn will manually generate the layout that the circuit engineer can use to verify the design. This process can take days or even weeks, and if there are any design changes that require multiple iterations, it can have significant impact on the schedule.

Animate is a fully-automated, transistor-level analog layout platform. It offers circuit engineers and layout designers an easy-to-use, automated layout flow that takes existing schematics, rapidly extracts constraints based on netlist topology analysis, and creates multiple DRC/LVS compliant floorplans for the supported PDKs.

Animate’s unique capability to create many electrically correct layouts from the input schematic in minutes enables circuit engineers to explore multiple layout options in a fraction of the time it takes a layout designer to produce a single layout by hand. With the ability to easily refine any of the generated layouts using Animate’s Blueprint Editor, the user benefits from the huge productivity gains of automation while still achieving the quality of layout demanded.

Layout ‘Wall’ showing multiple floorplans

Animate Handles Analog DRC/LVS Requirements

Analog design teams need high-quality results, automatic constraint handling and a flow that understands analog design and it’s complex DRC/LVS requirements.

Unlike DRC in the digital layout world, when only rule violations need to be detected and handled for the routing layers, analog design has to handle a much larger and more complex rule set. Automating analog layout needs to adhere to these complex rules as the layout is formed, and not having to rely on having some sort of post-layout fix up. Concurrent electrical awareness is required to ensure that the more complex requirements are met.

The Blueprint editor showing symmetrical device placement

Animate – a Modern Approach to Analog Layout Automation

Drawing on more than a decade of experience working closely with leading-edge custom design groups, Pulsic has developed an entirely new approach to transistor-level layout. Animate provides:

  • Automatic recognition of constraints such as matching, with corresponding placement heuristics to give, for example, common centroid matched structures.
  • Visual interaction of constraints in both the schematic and layout domains. Circuit engineers need to see them on schematics, layout designers on the physical level.
  • Rapid placement of devices and other structures like taps, dummy devices and guard rings to produce electrically correct layout while adhering to DRC rules.
  • Multiple layout choices are generated quickly using multi-threading, giving the designer a choice from which to make a selection and carry out any detailed analysis.
  • Blueprint Editor allows a high level of abstract editing of specific layouts such that structures can be moved relative to each other, guard rings added or edited, and dummy devices and well taps added.
  • DRC checks are built in to the PolyMorphic engine to produce DRC compliant layouts without the time-consuming Edit/DRC cycle of traditional polygon pusher layout tools.
  • Ease of use such that both circuit and layout design teams can generate initial layouts, and explore how changing device sizes (W/L/m factor/fingers) can give better matched or more compact layouts.

Pulsic’s Animate delivers a significant acceleration of the layout cycle, without relinquishing the level of control analog designers require.

Animate’s flow reads in a schematic, automatically extracts design constraints, and creates multiple layouts

Benefits

  • Get designers up to speed rapidly with minimal training and setup
  • Creates multiple, DRC/LVS compliant layouts in minutes
  • Generates all results in a fraction of the time of manual layout
  • Uses native OpenAcess and PCells or PyCells

Features

  • Easy-to-Use GUI
  • Automatic constraint recognition from schematics
  • Unique PolyMorphic Layout technology generates multiple electrically correct layouts ranked by user-specified criteria
  • Blueprint Editor to easily refine layout topologies as required

Benefits

  • Gets designers up to speed rapidly with minimal training and setup
  • Reduces layout time from days or weeks to minutes
  • Enables exploration of multiple architectures and extraction of realistic parasitics
  • Creates manual-quality results in a fraction of the time
  • Enables accurate simulation early in the design process
  • Uses native OpenAccess and PCells or PyCells

Features

  • Easy-to-use GUI
  • Automatic constraint recognition from schematics
  • Unique Polymorphic Layout technology generates multiple electrically correct layouts ranked by user-specified criteria
  • Supports CMOS analog (area-based) designs
  • Supports flat or hierarchical designs