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Products & Solutions

Pulsic Animate™

Fastest Route to Simulation-Ready Layout for Analog Designs

The complexity of layout for today’s advanced analog designs, especially those targeted at 90nm and below processes, has made automation a necessity for many design teams. Electrical issues such as layout-dependent effects (LDE), electro-migration (EM), voltage (IR) drop, and noise coupling have greater impact with smaller geometries. Automation can generate correct-by-construction layouts in a reasonable amount of time.

However, traditional analog design automation solutions are digital tools force-fitted to analog design needs. They do not help reduce design iterations or improve constraint handling between circuit and layout designers, which can be time consuming and error-prone. Also, these tools perform placement and routing as separate serial operations, producing sub-optimal results. In order to improve productivity and quality of results, an automation solution needs to quickly deliver multiple simulation-ready layouts with manual-quality results, automatic constraint handling and an easy made-for-analog design flow.

“Pulsic Animate is the first fully automatic layout system built from the ground up for transistor-level analog and custom-digital design. Animate offers an easy-to-use flow with automatic constraint extraction and unique Polymorphic technologies to produce multiple LVS correct, simulation-ready layouts in just minutes – guaranteed!”

Animate Delivers Productivity Gain

Animate provides circuit designers and layout engineers an easy-to-use, automated layout flow that takes existing schematics and rapidly extracts constraints based on netlist topology analysis. Animates creates multiple complete LVS correct hierarchical layouts in minutes. These simulation-ready layouts with better than PCELL parasitcs allow circuit designers to explore multiple layout options in a fraction of the time it takes a layout engineer to produce a single layout by hand.

Animate’s simple graphical user interface guides the user through the flow and enables the designer to visualize layout options quickly. Animate reads OpenAccess schematics, either hierarchical or flat, and automatically extracts constraints from circuit topology such as differential pairs, current mirrors and current sources. In addition, these constraints can be quickly edited by the user to customize their layout.

Animate’s flow reads in a schematic, automatically extracts design constraints, and creates multiple layouts

PolyMorphic Layout: Quality Results in Less Time

Animate employs patent-pending technology called PolyMorphic Layout, a novel database and algorithmic architecture to derive many potential layouts, which crystalizes into multiple LVS correct (Zero Opens/Zero Shorts) layouts. These multiple layouts are generated in just minutes so designers can explore various layouts and constraints with interactive speed.

Animate easily handles multiple levels of hierarchy

The process starts with the lowest-level leaf cells and moves up the hierarchy as cells are completed. Designers can lock the layouts that they want to keep, and these choices are automatically incorporated into higher levels within minutes. Animate generated layouts that are simultaneously optimized between placement and routing to produce high-quality results.

Breaking Down Bottlenecks

Animate’s Blueprint views allow designers to explore many possible layout architectures and extract early parasitics for simulation layout-dependent effects with minimal or no constraints. It helps designers to assess the impact of various parameters such as number of dummy cells, taps and routing layers and provide far more accurate analog block/design size estimation during floorplanning than ever possible previously.

Animate’s Blueprint view provides engineers early area estimations in the design process

As a circuit designer, the ability to automatically generate multiple versions of complete simulation-ready layout early in the design process enables them to verify their design and make quality trade-off decisions without waiting for final layout. Layout engineers can accelerate time to final layout by providing alignment constraints to control layout placement order for guided layout, as well as required layout topology to help speed up “Design Finishing”.

With Animate, transistor-level designers gain not only the productivity of automation, but also the ability to explore many design options faster than ever before. Most importantly, this is achieved in a fraction of the time as compared to manual layout implementation.

Benefits

  • Gets designers up to speed rapidly with minimal training and setup
  • Create multiple, complete simulation-ready layouts in minutes
  • Generates results in a fraction of the time of manual layout
  • Enables accurate simulation early in the design process
  • Uses native OpenAccess and PCells or PyCells

Features

  • Easy-to-use GUI
  • Automatic constraint recognition from schematics
  • Polymorphic Layout technology generates multiple electrically correct layouts ranked by user-specified criteria
  • Supports both CMOS digital and CMOS analog designs
  • Supports flat or hierarchical designs

Benefits

  • Gets designers up to speed rapidly with minimal training and setup
  • Reduces layout time from days or weeks to minutes
  • Enables exploration of multiple architectures and extraction of realistic parasitics
  • Creates manual-quality results in a fraction of the time
  • Enables accurate simulation early in the design process
  • Uses native OpenAccess and PCells or PyCells

Features

  • Easy-to-use GUI
  • Automatic constraint recognition from schematics
  • Unique Polymorphic Layout technology generates multiple electrically correct layouts ranked by user-specified criteria
  • Supports both CMOS digital (row-based) and CMOS analog (area-based) designs
  • Supports flat or hierarchical designs