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News

Press Coverage

EDN ( November 14, 2012)

Pulsic: The Bleeding Edge of Custom IC Design

December 13, 10:30am – 1:00pm

Pulsic AMS Chip Planning Lunch and Learn Event

EEJournal (May 31, 2012)

Pulsic Adds Guided Flows

SemiWiki.com (May 24, 2012)

After Planning Comes Implementation for Pulsic

EETimes (May 22, 2012)

Pulsic to introduce analog and custom digital place and route

EETimes

EEJournal Pulsic

SemiWiki.com (23-April-2012)

Channel Routing Memories

Pulsic Whitepaper (DesignCon 2012)

A Practical and Reliable Methodology for Hierarchical Signal Planning

EETimes

Top-level Custom Signal Planning and Routing

EDACAFE

New Unity Signal Planner and Router for Custom Designs

Chip Design Magazine

All I Want for Christmas Is a Capable Top Level Router

SemiWiki.com

Driving in the Bus lane

SemiWiki.com

The Requirements of Today’s Custom Signal Planning Methodologies

EE Times

Automatic shape-based routing to achieve parasitic constraint closure in custom design

DAC Knowledge Center

The Next Roadblock to Custom Design Productivity: Design Constraints

EDA Cafe

What will it take for next generation routing to meet the needs of the most advanced process nodes and beyond

EDA Online - Tech-on

Current Top-down approach for Mixed-Signal Design isn't good enough, Pulsic Pushes the boundaries of Mixed Signal Layout Design Domains <<Japanese>>

Earth Times

Si2 Announces Member Demonstrations at DAC

Electronics Weekly

Move to 32nm could force design change for chips

scdsource.com

Flash Memory Demands Custom Design Automation

EETimes.eu

Pulsic appoints former Cadence Japan exec to advisory board

electronicsweekly.com

Pulsic licenses flash design tool to Saifun

EETimes.eu UK

Pulsic, S3 and Runcom lead company search ranking

Electronic Design

Analog/Full-Custom Flows Move Toward Interoperability

edacafe.com

Pulsic's Custom Design Automation Solution to be Displayed at Flash Memory Summit

EETimes.com

Constraints open new EDA standards battleground

Edadesignline.com

Constraints open new EDA standards battleground

chipdesignmag.com

Pulsic advances placement and routing technology

EETimes.com

EDA looks to two good years in a row

EETimes.com

EDA 07 forecast: strong, but watch the bumps

powermanagementdesignline.com

EDA '07 forecast: strong, but watch the bumps

EDA DesignLine

Overcoming high-volume IC design challenges to maximise profits

Electronics Talk

Rocketing sales take Pulsic to top three

Embedded Computing Design

Pulsic is UK's Third Fastest-Growing Tech Company

EDA Geek!

Pulsic Ranks Third in Sunday Times Microsoft Tech Track 100

cieonline.co.uk

The ABC of EDA from DAC 2006

EETimes.com

Imperas tops analyst Smith's watch list

EETimes.eu

Oki uses Pulsic router to reduce layout design time

EETimes.com

Ness, Pulsic set up India development center

EETimes.com

Pulsic announces Unity physical design software

electronicstalk.com

IC design software adds advanced placement

EETimes.com

Pulsic adjusts EDA tool in response to customers

chipdesignmag.com

A new route to improving time-to-yield

electronicsweekly.com

EDA firm Pulsic supports SETsquared initiative

euroasiasemiconductor.com

Shaping the yield curve (Log in required)

EETimes.eu

EDA luminaries join Pulsic advisory board

chipdesignmag.com

Shape The Design of Wireless Chips

deepchip.com

INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2005"

EETimes.eu

Pati joins Pulsic board

EETimes.com

Numerical Technologies' founder joins board of EDA startup

chipdesignmag.com

Product News

EETimes.eu

Elixent uses Pulsic router for reconfigurable fabric ports

deepchip.com

DEATH TO VIRTUOSO! (Part III)

cieonline.co.uk

Hynix adopts Pulsic's place & route flow

EETimesUK

Place and route tool provides automation

edacafe.com

Pulsic Secures $5.5M First Round Investment

edacafe.com

New IC Routing Start-up Company - Pulsic - is Officially Announced

EETimesUK

Gridless IC router shapes up with combined effort